|09:00 ~ 10:00||참가자 등록|
|10:00 ~ 10:20||
Edge AI Technology Is Redefining Smart Devices: Present and Future
Nowadays, AI has been widely adopted in many real life applications such as smart speakers, surveillance and healthcare owing to the success of DNNs (Deep Neural Networks). DNNs achieve good accuracy at the cost of high computation complexity and memory usage. The ever-growing demands for privacy, short response time, and offline availability, create the trend of processing machine learning locally at the edge devices. Edge AI has been deployed to develop novel features or enhance performance of existing smart devices. It also brings new opportunities like home robots, real-time translation devices, etc. These demands are driving AI-powered devices to provide more AI computing capabilities. Generally, AI-enabled applications need the concurrent incorporation of DNNs with more tasks like image signal processing, 3D graphics, and wireless connectivity. The SoC design of AI-powered devices demands for technology breakthrough to meet these requirements under the resource constraints, especially in memory bandwidth and thermal budget. This talk will discuss the application and technology trends that are making smart devices truly intelligent.
|10:20 ~ 10:40||
Low Power Memory, Key Enabler of Intelligent Mobile and IoT Era
When the IoT was highlighted at the early of 2010s, interconnection among devices and small computing power were all about that technology. But now, as the AI (Artificial Intelligence) - whatever the types are - implemented as a default function from center to edge, computing power and data feeding have become much important than in the past. In this presentation, we will summarize the efforts what we have done for lower power consumption in memory, and propose for industry to define together what memory features would be needed for intelligent IoT era.
|10:40 ~ 11:00||
High speed AND low power DDRDRAM? Let’s do it with LPDDR4X!
The LPDDR4X standard is the latest evolution of low-power DDR DRAM. By reducing the I/O supply voltage from 1.1v in LPDDR4 to 0.6v in LPDDR4X, the I/O power can be significantly reduced. Despite the reduction in I/O voltage, LPDDR4X can achieve the full 4267MT/s data rate promised by the LPDDR4X standard, even in quad-die packages.This presentation will show how to take advantage of LPDDR4 and LPDDR4X in a range of applications from mobile to consumer to automotive, necessary features of the interface, techniques for achieving high speed LPDDR4/4X, and will show the design margin that can be achieved even with reduced voltage I/O.
|11:00 ~ 11:20||
UFS Card technology and challenges to achieve 1.2GB/sec performance
Every electronic product is connecting in 5G and AI era. Those numerous devices will generate Big data, and it required high bandwidth and high reliability removable storage. The UFS card product and Note PC supporting UFS Card is appeared in early of 2019, and it delivered near SSD performance. Now, it’s time to investigate all the details of advanced technology included in UFS card, in perspective why UFS Card shows superior performance with high reliability while consuming lower power. And, industry is already demanding the performance up to 1.2GB/sec for UFS Card. The solution architecture for IoT product vendors will be introduced with the real measure performance in real product.
|11:20 ~ 11:40||
Speed up your AI Designs with Dedicated Arm Machine Learning Hardware
Discover the features and benefits of Arm’s Project Trillium's hardware processors: Machine Learning (ML) and Object Detection (OD) processors, their software support, and applicability for different markets and the options for incorporating them in differentiating SoC designs. This talk will describe our strategy and plans for the highly scalable, ground-up designed ML architecture, the markets it will target and future product iterations. It will also include a comparison with other Arm solutions, enabling you to choose the best software and hardware combination to address your specific needs.
|11:40 ~ 12:00||
Enabling IoT Secure Programing
IOT products have been widely adopted in the automotive, home appliances and many other areas. These devices could be communicated via internet, radio transmissions which enable a free flow of the information exchange. However, this also induce the security risks and devices could be hacked or attacked. In order to manage the IOT security, device programing will play a vital role and emerge the discussion of “secure programing”. So far, there are different methods and methodology to enable “secure programing”, Dediprog will help to introduce the common methods and hopefully it could be further evolved and consolidated to be the industrial standard
|12:00 ~ 13:00||Lunch|
|13:00 ~ 13:20||
Memory Technology for Artificial Intelligence and IoT Automotive Applications
Dr. Gang Zhao(Huawei)
Memory technologies are faced with new requirement and challenges from the emerging AI and IoT automotive applications, ranging from bandwidth, power consumption, to reliability and safety. A comparative review of various memory technologies for AI and IoT automotive applications is presented. System design solutions and challenges are discussed.
|13:20 ~ 13:40||
DDR5 NVRAM, A New Wrinkle in Persistent Memory
Abstract: The evolution of DDR as a main memory interface is poised to move into the DDR5 generation. This protocol is fast, mostly deterministic, and widely adopted across many facets of the industry. While originally designed for the volatile SDRAM memory types, this protocol will also be adopted by a number of emerging non-volatile memories (NVMs) as well. The development of a new specification, DDR5 NVRAM, is under way to address this new class of “memory class storage”, devices that operate like an SDRAM but provide data persistence without the need for expensive and complicated battery backup systems. Controller designers will want to be aware of the benefits of a high performance persistent memory, such as the ability to turn off refresh in order to save power and increase data throughput!
|13:40 ~ 14:00||
UFS : Going Beyond Mobile
The UFS adoption in high-end and mainstream smartphones is robust and is now trending in other applications like automotive, digital home, imaging and AR/VR. UFS' high-performance, low-power consumption, and high-capacity advantages combined with multi-vendor availability make it an ideal solution for a variety of embedded applications. For example, Automotive ADAS applications require data storage for systems making near real-time decisions like a GPS, or digital home devices like set-top boxes require high-capacity, low-cost and fast storage solutions in small form factors. This presentation will highlight how UFS use cases are trending and are now seen in beyond mobile applications like automotive. UFS is a cost-effective solution since it is becoming more prevalent in the industry. The presentation will also explain some of the key design considerations that are important for SoC designers, with a focus on the importance of using automotive-optimized UFS IP.
|14:00 ~ 14:20||
Certifying UFS - The Leading Flash Technology for Mobile Open Standard Technology Created by JEDEC and Certified by UFSA
Mobile consumers are rapidly consuming more storage and more bandwidth and to keep pace with the ever changing landscape, Industry leaders got together in JEDEC to develop the open UFS standard for flash memory that would satisfy the needs and demands for now and well into the future. UFSA was formed to create a comprehensive compliance path for JEDEC standard UFS devices and infrastructure so suppliers could test their devices and users could have increased confidence the devices functionality and interoperability. As a non-biased industry consortium made up of suppliers and users, UFSA provides the framework for UFS infrastructure compliance and certification. The details of the organizations and how the infrastructure providers work together to bring quality to the end users certified by the UFS logo and the working committees
|14:20 ~ 14:40||
Assuring Customer Satisfaction and Competitive Advantage with the UFS Logo
JEDEC developed Universal Flash Storage (UFS) to succeed eMMC and support the next generations of mobile and IoT devices. Now UFS is beginning to show up in shipping products and an end-user installable card form factor is being defined by JEDEC. Products that take advantage of UFS’ new capabilities will achieve greater customer satisfaction and therefore a competitive advantage. It’s important that both system designers and end users know that UFS is included to provide improved performance, efficiency and price/performance flexibility. The UFS logo is the best way to let users know that they are buying a superior product. This session explains how products can earn the UFS logo and achieve the competitive advantages they expect.
|14:40 ~ 14:50||Break|
|14:50 ~ 15:10||
Enabling the Next Generation of IoT Edge Device Using MRAM
Jeff Lewis(Spin Memory)
IoT market forecasts predicted there would be untold billions of Edge devices deployed today. Why hasn't this happened? Even if consumer applications have been slow, massively-deployed monitoring should have been huge - putting smart monitors into everything from auto tires to soil moisture sensors. A significant inhibitor is the cost-benefit tradeoff for these devices. Conventional semiconductor technologies consume too much power - requiring more expensive batteries - and wear-out too quickly, requiring frequent replacement. This paper discusses how MRAM memories will drastically lower power consumption, improve endurance, and enable a new class of IoT Edge device.
|15:10 ~ 15:30||
Next-Generation Low-Power Memory Interfaces
Since the introduction of mobile DDR, or LPDDR, over a decade ago, the industry has continued to demand more of low-power memories, increasing their capabilities and pushing the limits of technology with each new generation. Today, the fourth generation of LPDDR (LPDDR4) is in volume production, and the industry is already looking ahead to the next generation of LPDDR. This session will provide information on the current state of the LPDDR5 specification development, including a look at some of the new features and functionality as currently defined.
|15:30 ~ 15:50||
Evolutionary Migration on LPDDR5
Jason Lee(SK hynix)
Current LPDDR4 mobile systems have reached their technical limitation. In this presentation, we can discuss the new requirements of the next generation mobile DRAM including density and bandwidth requirements. This presentation also contains the new features of LPDDR5 to represent these necessities.
|15:50 ~ 16:20||
UFS 3.0 & UFS Card 1.1: Controllers and Ecosystem Expectations
While the popular UFS 2.1 becomes the mainstream storage for mid-end smartphones, the next generation flagship/high-end segment has its spotlights pointed out to UFS 3.0. Offering approximately 2GB/s of performance, it makes for the ideal storage companion of late 4G and upcoming 5G-capable mobile devices. Meanwhile, the traditional mobile external storage continues to offer performances that lack behind and certainly degrade the user experience. While it is known that an alternative solution, based on PCIe, seems to be under development, the obvious solution for that problem resides on UFS Cards, which the specification ver.1.1 is derived from the UFS 2.1. These cards allow all the host and device makers to take advantage of the extensively tested and matured UFS 2.1 technology, safely contributing for a quick ramp up in their new removable storage solutions.
|09:00 ~ 09:55||참가자 등록|
|09:55 ~ 10:00||
Mian Quddus, Chairman(JEDEC)
|10:00 ~ 10:30||
Server Memory Architecture to Meet the Demands of the Next Decade
The mainstream server memory subsystem is under unprecedented pressure to deliver the memory BW needed by next generation Processors and IO and Fabric links, support emerging Storage Class and Persistent Memories, and Improve Reliability, Availability, Serviceability, and Security. This presentation will highlight key industry trends, explore looming and future challenges, and provide a peak at some of the architectural and ecosystem advances expected to be deployed in the decade ahead.
|10:30 ~ 11:00||
DDR5 Technology Overview, Opportunities and Challenges
Dr. Gang Zhao(Huawei)
A high-level review of new features in the DDR5 DRAM devices and DIMM modules for server and data center applications, including demand and challenges in various market segments and applications. A brief review of new testing system and methodology is also included
|11:00 ~ 11:30||
At the forefront of DRAM technology for better Datacenter Services
These days, there are many types of services to help / enjoy life such as SNS / Gaming / Education / Medical
Autonomous vehicle / etc.
|11:30 ~ 12:00||
Server Memory in the age of the Cloud
The challenges and solutions for memory modules as the world migrates to the cloud. Maximizing performance, density, channel resources, and expanding memory types all while balancing low power and low cost demands from the solution providers.
|12:00 ~ 13:00||Lunch|
|13:00 ~ 13:30||
Server Memory for Cloud to AI
The continuously changing application spectrum for servers and high performance computing forces diversification in system configuration for many customers. Configurable and flexible system architectures and memory subsystem designs are further demanded by a wide range of contemporary and emerging memory technologies. Adaptable, reconfigurable and heterogeneous memory subsystems are key factors for successful cost-performance optimization of next generation server systems.
|13:30 ~ 14:00||
Getting Ready for DDR5
In this talk we will discuss getting industry ready for DDR5. This includes DDR5 value prop, DDR5 component and module overview, JEDEC spec status, how we are getting ready, test and validation challenges, summary & call to actions.
|14:00 ~ 14:30||
NVDIMM-P for New Memory Ecosystem
Along with the Big Data era, many people in the server industry are talking about new memory and ecosystems. This presentation introduces several industrial approaches for adopting new memory and describes the basic concepts of the NVDIMM-P protocol that can use various new memory media in existing DIMM sockets.
|14:30 ~ 14:45||Break|
|14:45 ~ 15:15||
Gearing up to DDR5 for TCO Savings in Data Centers
Sam Byungsoo Kim(SK hynix)
In this presentation, server system trend, market trend focused on DDR5, key changes and value propositions of DDR5 will be highlighted, alongside few previous SK hynix public releases related to DDR5.
|15:15 ~ 15:45||
DDR5: Mainstream Memory That Maximizes Effective Bandwidth
The “data economy” is driving demand for higher-bandwidth memory due to increasing CPU core counts, frequency, and IPC. The explosion in compute capability magnifies the pressure on memory and storage, requiring more bits and higher bandwidth. Tiered solutions of memory and storage are the reality of the future. This presentation explains how DDR5 will make a difference for compute-intensive applications and provides examples of how DDR5 improves performance on specific workloads and enables real-world bandwidth improvements.
|15:45 ~ 16:15||
DDR5 DIMM Architecture & Eco System Overview
The complexity of DDR5 server memory sub-system has become ever so complex to meet the performance, capacity and power requirements for future generation of SoCs. This presentation will address all components on the DDR5 DIMM except for DRAM and how each component plays a role in delivering solution to future generation of SoCs and platforms. An overview of new approach to deliver power to the memory; to deliver reliable & high performance system management bus communication, DIMM temperature control and preview of security challenges and possible solution space is addressed in this presentation.
|16:15 ~ 16:45||
How Measurement Science informs the DDR5 specification
Over time, as DDR speeds have increased, the fundamental approach used to move data has had to change. Traditional High Speed Digital timing and noise with min/typ/max specifications gave way in DDR4 to High Speed Serial approaches based on eye masks with random and deterministic noise and jitter specifications. DDR5 must go a step further to deal with closed eyes using tunable equalization with the specification describing limits on the impulse response of the Tx/bus/Rx channel. At each point the need to characterize and measure what’s defined in the spec has made Measurement Science and DFT increasingly important in defining the DDR spec. This session will focus on the Measurement Science behind the DDR5 specification.
|16:45 ~ 17:15||
New Characterization Techniques for DDR5 Memory Generation and Beyond
With the 5G standard knocking on the door, datacenters will need to access a large amount of data at faster speeds and lower the power consumption at the same time. DDR5 provides double the bandwidth and density over DDR4 and delivers improved channel efficiency. Join Tektronix as we provide an update on the latest characterization and debug techniques to enable analysis of the highest DDR5 speed grades.